SPI based I/O expansion for CForth hardwareThis module is primarily developed to provide more I/O for the STM32F042 based CForth hardware proposal. Because the hardware resources of this controller are quite rare and are strictly pre-organized on this PCB, the circuit design had to care for some restrictions. So only one /CS line is available for 3 different ICs.
Anyway, this circuit can be used by almost any SPI with 3.3V supply and 3.3V data level or with 5V supply and 5 or 3.3V data level. Specifically it is compatible with the STM32G431 hardware proposal and as expansion for the small CForth operated DMX controller.
To make reconstruction as easy as possible, a single layer PCB with 2.54mm Veroboard compatible layout with standard through hole components is described here. Size 70x47mm.
The circuit works as follows:
The actual CForth firmware for STM32F042 provides a set of SPI signals at CN4: SCK=PA5, MISO=PA6, MOSI=PA7. Additionally /CN=PB1, +5V and GROUND are available at CN4, so the additional SPI module can be attached with a single connector. The "PB1inv" pin of CN4 could be used instead of T1, R4, R7 (see pinhead "2nd /CR" near pin9 of IC3). But for general fitness this was not used at the described circuit.
For use with other SPI master, unfortunately no SPI devices else can be operated with this construction. In this case, a separate /CR line would be needed for the 74HC595 instead of T1, R4, R7 (use pinhead "2nd /CR"), but the SCK pulses must be suppressed with T2, R4, R6 while this second /CR is high.
Veroboard compatible PCB design, size=70x47mm.
The layout is seen "through" the PCB from component side, as usually needed for PCB production.
CForth programming example for STM32F042:
//each data >9 is written with preceeding 0x,
//this way code is compatible with hex and decimal num base
//once init SPI and /CS idle state:
0xb1 oh //Port PB1 works as /CS
0 8 0x18 ini-spi; //about 100kHz clock with STM32F042
: limit dup 0xfff > if drop 0xfff endif ; //limit DAC input 12bit ( DacValue -- DacValue )
//0x3000 sets MCP4922 config bits for DAC A over input and split into 2x8bit SPI
//first SPI command returns CD4021 parallel input ( DacValue -- digIn )
: dacout 0x3000 | dup 0xb1 ol 8 >> spi swap spi drop 0xb1 oh ;
//send prepared output to DAC A, returns CD4021 parallel input ( DacValue -- digIn )
: dao limit dacout ;
//change config bit for DAC B
//send prepared output to DAC B, returns CD4021 parallel input ( DacValue -- digIn )
: dbo limit 0x8000 | dacout ;
//get parallel digital input from CD4021 ( -- digIn )
: pi 0xb1 ol nop 0 spi 0xb1 oh ;
//send parallel digital output to 74HC595 ( digOut -- )
: po 0xb1 oh spi drop 0xb1 ol 5 xnop 0xb1 oh ;
//simplified command to send parallel Out and receive Parallel In ( digOut -- digIn)
: pxch 0xb1 oh spi 0xb1 ol nop spi 0xb1 oh ;
* State of information August 2020.
* Right of technical modifications reserved. Provided 'as is' - without any warranty. Any responsibility is excluded.
* This description is for information only. No product specifications are assured in juridical sense.
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